Design Verification Engineer- Senior Associate- Technology

Tremend is looking for a Design Verification Engineer to join our team of bright thinkers and doers. You’ll use your problem-solving creativity to figure out our client s most complex and challenging problems across different industries. We are on a mission to transform the world, and you will be instrumental in shaping how we do it with your ideas, thoughts, and solutions. 

Responsibilities:

• Full front-end chip verification from verification plans to coverage closure
• A significant input in developing the next generation of core technology products for our customers
• Lead and mentor the young generation of verification engineers on the team

Qualifications:

• Good working knowledge of System Verilog and UVM
• Experience with interconnects and memory controllers is a plus
• Experience with third party VIPs in their verification environment is a plus
• SOC level experience is a plus
• Working knowledge of regression and coverage analysis tools is required
• Has developed an environment and taken a module to verification closure OR has significantly altered an existing environment and taken a module to verification closure
• Working experience with modern revision control systems: Git, Perforce, SVN
• Working experience with JIRA or similar ticketing systems